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GL830
產品簡述

The GL830 is a highly-compatible, low cost USB 2.0 / PATA to SATA bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver/receiver and Serial ATA PHY. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and Serial ATA specification rev. 2.6. There are totally 4 endpoints in the GL830 controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL830 can support not only plug and play but also Windows Vista/ XP/ 2000/ ME default driver. The GL830 uses 25MHz crystal and slew-rate controlled pads to reduce the EMI issue.


GL830 provides four package types –LQFP 48pin (7x7mm), LQFN 46pin (4.5x6.5mm), LQFP 64-pin (7x7mm) & LQFP 128-pin (14x14mm) for different target applications.


1. LQFP 48pin package provides basic USB to SATA bridge function to fit standard USB 2.0 high speed storage class applications such as SATA HDD and ODD enclosure. It provides the best cost / performance solution in industry. In terms of cost, GL830 features on-chip 5V to 3.3V regulator and low pin count package to minimize overall system cost. In terms of performance, GL830 provides industry-leading data read / write speed and latency that powered by internal turbo 8051 micro processor. In terms of power consumption, GL830 features low-power mixed signal design to reduce silicon operating current. It also provides various power management options for system designer to reduce system level power consumption.


2. LQFN 46pin package provides the same function / performance as LQFP 48pin. It features smaller silicon foot print and lower silicon operating temperature, which is perfect for mechanical limited PCB design.


3. LQFP 64pin provides an additional SATA differential pair that enables USB / E-SATA (External SATA) to SATA function for HDD enclosures with both USB and E-SATA port. It features on-chip SATA switch that provides both E-SATA to SATA and USB to SATA data path in one single chip.


4. LQFP 128pin integrates USB, PATA and SATA interface into one single chip. PATA interface can be configured as host or device that meet system requirement of various applications. For example, when PATA is in device mode, GL830 can be connected to embedded system’s legacy IDE port to serve as a multi-IO bridge for USB and SATA connection. When PATA is in host mode, GL830 is a USB to PATA
and SATA bridge that enable concurrent data transfer on both USB to PATA and USB to SATA path.

 

48 / 46 / 64 / 128pin feature comparison

Applications

48pin

LQFP

46pin

LQFN

64pin

LQFP

128pin

LQFP

USB host to SATA HDD / ODD
USB / E-SATA host to SATA HDD    
USB / E-SATA / PATA host to SATA HDD      
USB host to PATA + SATA IF cable      

 


Complies with Universal Serial Bus specification rev. 2.0. (USB-IF test ID – 40000391)
Complies with USB Storage Class specification ver.1.0. (Bulk only protocol)
Operating system supported: Windows Vista32&64/XP/2000/Me/98/98SE, Mac OS 9.X/10.X, Linux Kernel 2.4.X/2.6.X. (Windows Submission ID : 1273643)

Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE)
Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3)
64 / 512 bytes Data Payload for full / high speed Bulk Endpoint
Complies with Serial ATA specification rev. 2.6
Support SATA II asynchronous signal recovery feature(hot-plug)
Compliance with Serial ATA II Electrical Specification 1.0
Complies with ATA/ATAPI-6 rev. 1.0 (only available for 128pin package)
On-chip SATA switch for E-SATA to SATA data path (only available for 64/128pin package)
Support Spread Spectrum Clocking to reduce EMI
Support Partial/Slumber power management (optional)
Support hard-disk power management feature (optional)
Support hard-disk write-protect function (only available for Windows XP/Vista, supported on 830-12 and later version)
Support hard-disk lock/unlock by EEPROM Key feature (complementary feature with Genesys Secured
Backup software)
Provide adjustable TX signal amplitude and pre-emphasis level
Provide specified OOB signal detection and transmission
Embedded Turbo 8051
On-chip Watch Dog Timer for auto error recovery (Supported on 830-12 and later version)
ROM size: 24K bytes; Bulk Buffer: 1K
Supports Power Down mode and USB suspend indicator
Supports USB 2.0 TEST mode features
Supports 4 PIO and 4GPIO for programmable AP
Provides LED indicator for Full Speed and High Speed
Single 25 MHz external clock input
3.3V power input; 5V tolerance pad
Embedded Regulator (3.3V to 1.8V)
Embedded Regulator (5V to 3.3V)
Provides SPI interface for Finger Print (only for 128 pin package)
Available in 48/64/128-pin LQFPand 46-pin LQFN


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